1. Field of the Invention
The present invention relates to a process of making a semiconductor device. More particularly, the present invention relates to a process of fabricating a deep trench capacitor of a dynamic random access memory (DRAM) device. According to this invention, the shallow trench isolation (STI) regions are fabricated prior to the formation of the deep trench capacitors.
2. Description of the Prior Art
As the size of a memory cell shrinks, the chip area available for a single memory cell becomes very small. This causes reduction in capacitor area and therefore becomes a challenge for chip manufacturers to achieve adequate cell capacitance. Trench-capacitor DRAM devices are known in the art. A trench-storage capacitor typically consists of a very-high-aspect-ratio contact-style hole pattern etched into the substrate, a thin storage-node dielectric insulator, a doped low-pressure chemical vapor deposition (LPCVD) polysilicon fill, and buried-plate diffusion in the substrate.
The doped LPCVD polysilicon fill and the buried plate serve as the electrodes of the capacitor, wherein the polysilicon fill is typically referred to as a storage-node electrode. According to the prior art, a dielectric isolation collar disposed at the upper region of the trench is essential for preventing leakage of the signal charge.
Please refer to FIG. 1 to FIG. 11. FIG. 1 to FIG. 11 are schematic cross-sectional diagrams showing the fabrication process of the trench capacitor DRAM according to the prior art. As shown in FIG. 1, firstly, deep trench structures 11 are formed in the semiconductor substrate 10. The formation of deep trenches is known in the art. For example, a hard mask stack consisting of a pad oxide layer 12, a pad nitride layer 14, and a thick borosilicate glass (BSG) layer 16 is formed on a main surface of the semiconductor substrate 10. Thereafter, a conventional lithographic technique and etching process such as reactive ion etching are carried out to form the deep trench structures 11.
As shown in FIG. 2, after removing the remaining BSG layer 16, an arsenic silicate glass (ASG) layer 22 is deposited on the interior surface of the deep trench structures 11. The ASG layer 22 is also deposited on the pad nitride layer 14. A photoresist layer 24 is then formed at the lower portion of each deep trench structure 11. To form the photoresist layer 24, a layer of photoresist is coated on the substrate 10 and fills the deep trench structures 11. The photoresist is then etched back. The ASG layer 22 that is not covered by the photoresist layer 24 is removed from the sidewalls of the deep trench structures 11 and from the surface of the pad nitride layer 14.
As shown in FIG. 3, a thermal process is carried out to drive dopants, in this case, arsenic, from the ASG layer 22 into the adjoining substrate 10, thereby forming a buried N+ diffusion plate 25, which serves as a first electrode of the deep trench capacitor. Thereafter, the photoresist layer 24 and the ASG layer 22 are removed by methods known in the art.
As shown in FIG. 4, a capacitor dielectric layer 27 such as an oxide-nitride (ON) or an oxide-nitride-oxide (ONO) dielectric film is formed on the interior surface of the deep trench structures 11. A first polysilicon layer 29 is then formed in the substrate 10. The first polysilicon stud 29 has a top surface that is much lower than the surface of the substrate 10. To form the first polysilicon stud 29, a layer of CVD polysilicon layer is deposited on the substrate 10 and fills the deep trench structures 11. The CVD polysilicon layer (not shown) is then etched back to form a recess at the upper portion of each deep trench structure 11. This process is also referred to as first poly deposition and recess etching process. The exposed capacitor dielectric layer 27, which is not covered by the first polysilicon stud 29, is then removed.
As shown in FIG. 5, a collar oxide layer 32 is then formed on the upper sidewalls of the deep trench structures 11 above the first polysilicon stud 29. A second poly deposition and recess etching process is carried out to form a second polysilicon stud 34 in the deep trench structure 11 on the first polysilicon stud 29. The formation of the collar oxide is known in the art. For example, a CVD oxide film (not shown) is deposited on the interior surface of the deep trench structure 11. The CVD oxide film is then etched back.
As shown in FIG. 6, the exposed collar oxide layer 32, which is not covered by the second polysilicon stud 34, is removed so as to expose the substrate 10 at the upper portion of the deep trench structure 11 and to form a recess 36 at the top of each deep trench structure 11.
As shown in FIG. 7, a third polysilicon stud 44 is formed in the recess 36. The third polysilicon stud 44, which has a top surface that is lower than the surface of the substrate 10, is formed on the second polysilicon stud 34. A chemical vapor deposition process is performed to deposit a borosilicate glass (BSG) layer 46 on the substrate 10. The BSG layer 46 fills the recess 36.
As shown in FIG. 8, a lithographic process is carried out to form a patterned photoresist layer 48 on the BSG layer 46. The patterned photoresist layer 48 having an opening 50 defines the shallow trench isolation area. The pattern of the photoresist layer 48 is then transferred to the underlying BSG layer 46 and the pad nitride layer 14 using a conventional anisotropic dry etching process.
As shown in FIG. 9, using the remaining photoresist layer 48 and the BSG layer 46 as an etch hard mask, an anisotropic dry etching process is carried out to etch the pad oxide layer 12, the substrate 10, the third polysilicon stud 44, the upper portion of the second polysilicon stud 32, and the upper portion of the collar oxide layer 32 through the opening 50, thereby forming an STI opening 52.
As shown in FIG. 10, after removing the remaining BSG layer 46, The STI opening 52 is filled with a high-density plasma (HDP) oxide film 56. Finally, as shown in FIG. 11, a conventional chemical mechanical polishing (CMP) process is carried out to polish the HDP oxide film 56 to a pre-selected thickness.
In general, the above-described prior art method for fabricating a trench capacitor of a DRAM device can be summarized as follows:
Phase 1: deep trench etching.
Phase 2: buried plate and capacitor dielectric formation.
Phase 3: first polysilicon deep trench fill and first recess etching.
Phase 4: collar oxide formation.
Phase 5: second polysilicon deposition and second recess etching.
Phase 6: third polysilicon deposition and third recess etching.
Phase 7: STI process.
It is disadvantageous to use the above-described prior art method for fabricating a trench capacitor of a DRAM device because the prior art processes are complicated and time-consuming. According to the prior art, it needs three stages of polysilicon deposition (poly 29, 34 and 44) and the subsequent recess etching to complete the capacitor electrode situated within the deep trench. Further, as each capacitor cell area shrinks, the thickness of the collar oxide has negatively affected the effective space for depositing the second polysilicon stud 34, and therefore results in raised capacitor resistance and reduced memory operation performance. In a worst case, the CVD polysilicon cannot be deposited into the deep trench because the thick collar oxide narrows down the dimensions of the upper portion of the deep trench.
Moreover, when defining active areas and shallow trench isolation regions, misalignment might cause capacitor disconnection from the pass transistor/gate thereof because signals cannot be transmitted to the storage node through the collar polysilicon stud 34. Furthermore, it is difficult to develop a suitable etchant recipe for etching the complex structure within the STI regions.
Accordingly, there is a strong need for an improved method for making deep trench capacitors of DRAM devices which is not complicated and has good yield and reliability.